Monthly Archives: July 2015

37 Class C Part 4 Focussed Modulator Design

The story so far:

After proposing pulse width modulation of the input signal of a Class C stage to determine the amplitude on the output, I showed that if we used a simple pulse width modulator that varied the pulse width in proportion to the instantaneous value of the baseband signal voltage, we got a distorted result.

I postulated two approaches to fixing this in Post 35. The first was negative feedback and the second was “smarter modulator”. I showed how effective feedback can be in Post 36. Now we turn to the “smarter modulator”.

The short version is that the output (in real life – high powered) tank circuit is mimiced with a low voltage LC circuit. This circuit is fed with a variable width pulse to maintain the amplitude close to that of a reference signal obtained by amplitude modulating a representation of the carrier with an analogue multiplier.

I will provide particulars and then show the result.


There are two steps.

First, the carrier signal is processed to generate various special signals that are required by the modulator proper.

It will be easier to find what follows clear if it is remembered that the tank circuit has the property that the quasi sinusoidal on it is placed so that the driving pulse falls on the positive going zero crossing.

1 Tank waveform

The first signal generated is a signal I call “dual_slope”.

The signal has a notch shape that is centred on the positive going zero crossing of the carrier.

2 Dual_Slope

This could be generated in any number of ways. If you are interested, this is how I did it.

3 Timing triangle generator

The second is a pulse “Sample” that occurs during the time when the carrier is near the most negative value. This pulse is accurately centred on the time when the carrier is at exactly the minimum value. See the blue trace below. The third is a pulse of less critical timing “Clear” that occurs later.

4 Sample and Clear

As before, I won’t go into the details of how these pulses are generated, but will show my model schematic for those interested.

5 Sample and Clear generation

The only other signal required for the modulator is a representation of the amplitude modulated signal that the Class C stage is to produce. Of course in this low level signal modulator board, this is easy to do with an analogue multiplier IC.

6 Analogue multiplier modulated carrier

Second Step
Now we come to the actual Pulse Width Modulator for Low distortion Class C stage.

7 Modulator

It is easiest to describe the operation of this when it is already running. It is easy enough to extend this to graceful start-up. I will leave that to the imagination of the reader.

To the right of the circuit diagram there is a tank circuit and an exciter arranged just as I have arranged these in previous Class C stage models. The idea here is that these are all small signal components on the “modulator board”. It has appeared later that there might not be any reason for this “Mock Tank Exciter” and “Mock Tank”, as the actual exciter and tank could play the role here. I will leave this as it is for this explanation.

The voltage on the Mock Tank is compared with the modulated signal from the analogue multiplier at the voltage controlled current source G3. This then provides a current that is proportional to the difference. This current is shunted away by diode D1 or diode D2 except when the voltage controlled switch S11 is closed during the “Sample” time.

8 Modulator waveforms

The voltage on the Mock Tank circuit is the brown trace. The reference modulated carrier is the blue trace. It will be seen that the magnitude of the reference modulated carrier is greater at the negative excursion. During the Sample time (red trace) the current representing the difference is used to charge capacitor C6. At the end of the Sample pulse, the charge on C6 represents how much the Mock Tank circuit is falling behind the reference signal. This is then used to determine the duration of the pulse of energy imposed on the tank by the exciter in the following cycle. C6 is discharged on the Clear pulse (not shown) The voltage on C6 is converted to a width of a pulse that is properly centred so as not to introduce phase modulation by comparing it with the dual_slope signal.

9 Pulse width modulation

Here the DS_Offset (Which is “dual_slope” with an offset added) is shown in brown. The voltage on the capacitor C6 is green as before. The blue trace shows the excitation signal for the Mock Tank. It is high whenever the C6 voltage is higher than the voltage of “dual slope”. It can be seen that this scheme will provide a variable pulse width to excite the tank, and that the width will vary as required to provide just enough energy to the Mock tank to have its voltage fall just a little behind that of the reference signal. At the same time, the driving pulse is properly timed so that there will be no phase variation as the amplitude is modulated.

I am writing this up many weeks after I developed the model. There are various reasons for regarding this as unnecessarily complicated. The complication would all be accounted for in a very small board area of small signal circuitry, so would be readily born if it gave the best result. What result does it give?

10 input vs demod

The red trace is the base band signal at the very input to the model.

The brown trace is (with attenuation and offset) the output of a synchronous demodulator on the high powered tank circuit.

One way to check for linearity is to modulate with a slow ramp and look for the straightness of the ramp on the output. here is what we get.

11_sawtooth that is better

The brown trace is the input to the modulator, and the blue trace is an attenuated version of the output from the demodulator. That is linear!

Compare this with my initial “crude” pulse width modulator in which the pulse width is proportional to the voltage.


36 Class C Part 3

36 Class C Part 3 Feedback around Modulator

The story so far:

I have investigated the idea of a “Class C” amplifier and pushed the notion that the feature that the active device conducts for less than half the cycle is not definitive. It seems much more important to dwell on the high efficiency amplification without regard to distortion, and then recovery of the wave shape afterwards. In AM or CW transmitter service, the recovery is carried out by a high Q tuned circuit called the “Tank Circuit.”

Although possibly not available to “old time” circuit designers, the idea that a high efficiency active device that is working as a switch, could be modulated with pulse width modulation seems attractive. Unfortunately a very simple modulator that gives pulse width proportional to signal gives a distorted amplitude modulation envelope.

Here is the waveform that I obtained when I modelled a circuit consisting of these stages:

1. Pulse width modulator
2. Switching Power Stage
3. Tank Circuit
4. Diode demodulator.
Pulse width modulated sine simple waveform

The brown trace is the modulating waveform, and the blue trace is the output from the demodulator. Note that the blue trace is much “broader” on the positive excursions than on the negative ones.

See my Post “35 Class C part 2”.

It was evident that the simple law chosen for the modulator was not right for the characteristic of the tank circuit in changing pulse width back into sine wave amplitude. I suggested two remedies. The first, was to put negative feedback around the whole modulator – power amplifier – demodulator system: the second was to design a pulse width modulator that varied the pulse in a way that would give the correct result at the Tank Circuit.

Today’s post is to explore the first: Negative Feedback.

Here is my model circuit:

Feedback diode circuit

The demodulator is the diode demodulator we saw in the last post. I mentioned then that I added L2 in series with C2 to make a trap as I wanted to reduce the carrier, but did not want to put filter poles where they would interfere with my feedback loop. Notice the resistive divider R3, R4. This reduces the asymmetry that one gets if a shunt capacitor is placed directly on the cathode of the diode. In such a case, the diode charges the capacitor quickly, but it will discharge much more slowly. In this circuit, C3 and C2 are charged and discharged with much more similar resistances.

That’s the logic of it anyway. Probably completely invalidated with the addition of the series LC trap. Maybe diode demodulators is a subject for another day.

The resistive divider on the Modulation signal giving the signal Modbuf is just there so that we can see an input signal and an output signal that are similarly scaled.

Here are the traces.

Feedback diode modulator traces

It is easy to see that the output signal is very much less distorted than without the feedback. As the output waveform is not created with a continuous process (the pulse width modulation), I cannot simply run a spice FFT on the output to measure.

I calculated the phase shift of the base band signal as it found its way along the forward path. The actual amplitude modulation of the carrier at the tank circuit is lagging the modulating signal by about 2.2 degrees. The output of the demodulator is lagging the modulating signal by 30 degrees.

I tried substituting a synchronous peak detector for the diode detector. This effectively gave me a sample and hold on the peaks of the full wave rectified modulated waveform. This gave me a minimum ripple and enabled me to reduce the low pass filtering required for a smooth baseband signal. The result is shown below. You will see that the brown trace (output of demodulator) lags behind the blue trace (modulating signal) very much less with the synchronous demodulator.

sync demod