Category Archives: Uncategorized

Post 42 Two and a Half Times Part 2

There has been a delay of many months in getting this blog post out the door. This has not been because of flagging interest, but the opposite: there have been interesting revelations and discoveries that have caused the goal posts for this write-up to move about. Several times, I had thought that this post was complete, and then new information came in, or a new insight was gained that seemed to redefine the problem.

The factors that have come to bear, fall (in part) outside the scope of this blog, as I have tried to keep this blog focussed on the technical aspects of electronic engineering. The subject of how to order the affairs of an engineering team for synergistic productivity has been kept aside for publication in a different forum. However we can never really divorce the consideration of how we design something from the consideration of how that design task will fit into an overall plan.

I will touch lightly here on one aspect of project management that has had an impact in this case. This is risk management. Almost by definition, until some development work has been performed, we do not know what the outcome will be. If we knew the outcome in every detail, there would be no development work to do. One possible path through the development work is that a design approach is thought up and documented sufficiently for a prototype to be made. Testing of the prototype will yield results that might:

(a) Prove that the idea is without flaw and can be incorporated into the design without modification.

(b) Show that the idea is workable, but that changes have to be made in breathing life into the prototype. These changes might represent a discovery that there was a mistake in the concept, or a mistake in the documentation that served to represent an invocation of the concept.

(c) Show that the idea is not suitable to proceed with.

Of course, one hopes for an (a), but one has to be prepared to proceed with the project whatever the outcome of the prototype building and testing (the “technicianing”) effort.

Note that if no competent technicianing effort is brought to bear, then the conclusion will be that we have a (c). This might be an error, and a really good (a) or (b) opportunity can be missed.

It falls to the project manager to conduct realistic risk analysis before the technician sets to work, and to have plans up his sleeve for all outcomes. Part of his work is to evaluate the competence of the technician workforce. If the technician assigned cannot distinguish between a failure on his part, and a failure of the concept, then a different plan is called for.

During explorations with spice during the preparation of this blog post, I discovered a simple mistake in a concept implementation that I had made in 1987. [Spice was not available (to me) at that time. The first implementation of spice that stepped out of the mainframe/Fortran environment seems to have been released in 1985. (See here.) Another reference says 1989, but it looks as if that can’t be right. James Fenech has a “Pspice” book that is dated 1988. In my next job, (1988) I was using MC3, an early schematic entry based spice invocation.] The mistake was immediately obvious, and very easy to fix. It would have been very obvious, and easy to fix by the person charged with the task of getting the prototype going in 1987.

The concept described in this blog post was wrongly categorized as a (c) in 1987 by the team technician and my boss. A big mistake.

Here we go then:

My second example of the exploitation of the relationship of two frequencies in the ratio of 2.5 to 1 is also a communications one.

The application was a network of stations that were to be linked by radio. There was one central station which was to gather information from all the others. Some radio links were short and could be expected to provide a strong low-noise signal at the receiver. Other links were longer or involved difficult paths, and were expected to present a noisy or degraded signal at the receiver. We were aware that it would take more time to send an error free packet of data down a noisy and degraded link than through a high fidelity one.

The amount of traffic was such, that it looked as if we could not slow the traffic down on all links to meet the needs of the worst one. We needed a system with a variable bit rate. The rate on each link could be set at commissioning time, or (and this was my hope) set dynamically to adjust to the needs of each link. Dynamic bit rate adjustment might require expensive or tricky software. We did not have any idea of an algorithm for it. It looked as if “set up” bit rate for each channel would be workable, if not complying with all my flights of fancy.

Many readers in this forum know the difference between bit rate and symbol rate. For those who are not quite clear on this, here is a brief diversion.

The symbol rate, for which the unit is the baud, (pronounced “bode”) is the rate at which data are passed. Each datum, however can carry more than one bit of information. The number of bits per symbol need not even be an integer. Imagine a channel that transfers equally likely symbols that are a number between 0 and 9.

Number of choices, N = 2n where n is the number of bits.

n = log2(N) = ln(N)/ln(2)

= 3.321928

At first, it might look like a really difficult problem to deal with symbols with that number of bits each, but it is in fact very easy.

1. Look at the first symbol

2. Get the value of the symbol.

3. Multiply by 10

4. Add the next symbol symbol

5. Loop back to step 3. until the end of the message is reached.

I first encountered a simple and practical application of a non-integer number of bits in the Digital Equipment Corporation Radix-50 system. https://en.wikipedia.org/wiki/DEC_Radix-50

In this system, characters were drawn from a character set of 40 characters

(space, A, B, C, D. E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U, V, W, X, Y, Z, $, ., %, 0, 1, 2, 3, 4, 5, 6, 7, 8, and 9). Forty is “50” when expressed in Octal, the preferred numbering on DEC machines; hence the name. The number of bits of information embodied on one of these characters is 5.3219 (or thereabouts). Packing three of these characters into a 16 bit word is very simple.

(using decimal notation)

The characters are assigned values from 0 to 39

Take the first character and multiply its value by 40

Add the second character.

Multiply the sum by 40

Add the third character.

The maximum value of the result is 63999. This is less than 65535, the maximum value we can store in 16 bits (binary 1111 1111 1111 1111), and will thus fit in a 16 bit word.

Extracting the characters is easily accomplished by dividing by 40 a couple of times and saving the remainders. All this was worthwhile in the days when non-volatile memory was made of magnetic cores, and a 32k x 16 memory board was a big expensive memory!

In a variable bit rate system, it is a simple matter to vary the multiplier to suit the number of choices represented by the symbols in each link.

[Note that we might regard this as an extension to the simplified concept we apply when we say (for example) that an LS74374 is an eight bit register. We say this without regard to what information it might hold in any particular implementation. If it only ever holds the ascii representations of the numerals 0 to 9 then there is a sense in which it is a 3.321928 bit register. The use of bit is thus context sensitive. I have never seen this lead to ambiguity. There is a third level of sophistication that we could apply when we consider the probabilities of occurrence of the particular values (following Shannon). The communication system being described here employed a layered architecture, and the layer being considered (lower layers) did not have information about the meaning of the data that was being handled, or the probability of occurrence of any particular values.]

The data was encoded by phase shift keying a tone with a frequency that was placed in the middle of the baseband. This was 1650 Hz. The symbol rate was 660 bauds. The time required to set up the carrier with a new phase, and let the bandwidth limited channel settle and then measure the phase at the receiver end was just 2.5 times the carrier period.

The receiver was phase locked to a pilot tone with a frequency at the symbol rate, that is 660 Hz. The symbol time was divided up like this:

In this receiver the channel was gated so as to accept only the last two fifths of the symbol time. The gate period is exactly one cycle of the carrier frequency. The symbol data is determined from the timing of the positive going zero crossing during that time. This was done with a technique that I think I must have pinched from Ed Cherry’s “Omtrack” Omega receiver. An eight bit counter is clocked at 256 times the carrier frequency. When a trigger circuit detects the positive going zero crossing, the contents of the counter are transferred to an eight bit latch.

The pilot tone will add some error, although this could easily be corrected for by cancelling it out. In the first instance, (pilot tone 15 dB below carrier) we showed that the system would work without correction.

One task was the establishment of message timing at the receiver. This was a task for which an approach was proposed but several back up approaches were formulated in case there were problems with the first.

The proposed message format consisted of an initializing period during which a 660 Hz (symbol rate) pilot tone was transmitted at the maximum amplitude provided for by the channel. After sufficient time for the receiver phase locked loop to capture the message pilot tone phase trajectory, the pilot tone amplitude was reduced to a small fraction of the initial amplitude, and the receiver phase locked loop speed was reduced, as from then on it only had to correct for errors due to phase drift, a low frequency phenomenon.

I knew less about feedback loops then than I came to know later, and the provision I made for adjusting the speed of response of the phase locked loop (fast for acquisition: slow for phase maintenance) was very naïve by the standards of today. I used CMOS switches to select between two different loop filter alignments. Interestingly, I have seen that “naive” scheme published by others, so I was not the only one to miss an opportunity. Perhaps varying the speed of a control loop could be the subject for another blog post (but see below).

The interesting trick is that the gate circuit which passes the channel signal for exactly one cycle of the carrier, also forms the first block of a neat phase comparator for the phase locked loop that keeps track of symbol timing. This phase comparator has very good resistance to interference from the carrier. The signal from the gate is fed to an integrator. Over the one carrier cycle time, the net contribution to the charge on the integrator from the carrier is zero. The sample of the pilot tone, is however a measure of the phase error. The output of the integrator is captured at the end of the integrate time by a sample and hold circuit.

I have shown the narrow “Sample” pulse occurring right at the end of the integrate time. Of course, the integrate time could be brought to an end, and then the static voltage on the integrator sampled after that. Analysis showed that this was not necessary. The situation is analogous to an A/D converter following an amplifier with no sample and hold. If the slewing rate of the amplifier output is low enough, and the A/D is fast enough, the special saving of a static value is not required.

This is the block diagram of the “Carrier Immune Phase Comparator”.

For this phase comparator, we have:

RC is the time constant of the integrator.

Note that this expression has two components that depend on the pilot tone signal. θ is the phase error, and a is the amplitude. If we like, we can represent these as being introduced to the loop separately. That is, we can take a out of KD and apply it to the loop separately.

You can see that the (B) block diagram representation is the same as the (A) representation, except that the θ and the a components are shown separately. This clarifies an interesting point. There is a multiplier in the loop, and the loop gain depends on the amplitude of the pilot tone.

Here I show a “canonical” phase locked loop representation on which I have added the signal names from the discussion above.

If the loop filter has a characteristic which has falling gain with increasing frequency (which it will inevitably have), then the speed of the loop will change as the loop gain changes.

Here I show an arbitrarily chosen loop filter characteristic. The brown line represents the loop gain that we would have during the initializing period when the pilot tone is at full strength. The blue line represents the loop when the pilot tone has reduced by 15 dB during the data transfer part of the message. This means that a has reduced by a factor of 0.178. Note that as the loop gain is reduced (Arrow 1. on diagram), the unity gain crossover frequency is reduced (Arrow 2. on diagram) by a factor of 3.2/16 = 0.2 (which is about 2.3 octaves)

The red line is the pilot tone frequency.

I was very pleased with this phase comparator concept, although these days, I would approach that original problem very differently. It seemed to me that the line of thinking behind this phase comparator might have other applications, and indeed this has been the case.

Blog Post 41 Two and a Half Times 1B bis

10-01-2017       Happy New Year!

I thought I had done with “Two and  Half Times 1B”, but recently, I was sorting some old papers and I found circuit diagrams of the receiver that I described in the last post. A lot of what I reported in Post 40 was from memory, so it is interesting to see this material and see how good my memory has been. If you are coming here from scratch, this won’t make much sense, so read Blog Post 40 first.

To present this blog to you, I use “Word Press”. This seems to have lots of nice features, but it does limit the width of the part of the screen that I can use for diagrams. For those of with moderate screens, I wanted to use 100% of the screen width, so I have stepped out of WordPress for this.

To read on, follow this link here

Blog Post 40 TWO AND A HALF TIMES PART 1B

HYTECO DRIVERLESS TRACTOR SYSTEM MODEMS            14-09-2016

It has been some time since the last post, so I will reiterate the background to this one. The context is a requirement for two way communications between driverless tractors following a wire guidepath set in a warehouse concrete floor. In the last post, I discussed the traffic from the central controller to the tractors, which we called “down” traffic. As the carrier for the data signal could be of large amplitude, the only limit being that it did not interfere with the tractor guidance system, we had no trouble getting the signal up out of the noise. We used frequency shift keying using off-the-shelf PLL chips. The frequency deviation was determined by the chip manufacturers. It was not ideal for our purposes but it worked. This was all described in the last post.

In this post I turn to data traffic from a tractor to the central controller (“Up” traffic).

The tractor transmit antenna was designed by Roger Riordan. I have described this in this blog before (“Time Passes 1” posted in August 2013. You can find it easily by placing “Riordan” in the search box.). This was a second attempt: the first was an un-tuned transmit coil driven by a square wave at carrier frequency. This was unsuccessful, and could probably have been made successful, but when I called Roger Riordan in, he wanted to do it “his way” and I (wisely) let him meet the requirements in whatever way he liked.

He chose the Class C output stage with his clever tuning scheme. There was a potential problem with the idea of a tuned antenna. A portion of the magnetic circuit was through the concrete floor. We had discovered that at the sorts of frequencies we were dealing with, the permeability of concrete is much higher than μ0 and varies between concretes with different aggregates. The tractors had to work over the floor of an old building and a new building, so the tank circuit antenna might have detuned a bit as the tractor moved from building to building. It was fortunate that we didn’t waste time worrying about this, as that would have just wasted time. I realise now, as I am writing this about 38 years later, that the difference in the different concretes might have caused a problem that we faced – and then solved later on.

Riordan’s choice of a Class C stage with tuned tank came after my decisions about modulation scheme. The Riordan antenna design does not have the bandwidth to carry the FSK type of signal used for the Up traffic.

I had been concerned about bandwidth for a completely different reason. The receiver had to pick out a small signal from a channel with other large signals on it. One aspect of our efforts to find the signal in amongst all the noise was to place the signal in a quiet place in the frequency spectrum, and use no more bandwidth than necessary. The FSK encoding used for the Down traffic had to use much more bandwidth than the theoretical minimum, as the characteristic relationship between frequency and voltage at the phase locked loop chip VCOs, and the need for voltage swing dictated a large difference between the frequencies representing mark and Space. A different scheme was called for.

When the signal is weak, and of narrow band, it become important to synchronize the transmitter and the receiver. The scheme chosen was to use frequency synthesizers clocked from the guidepath signal at the Tractor and at the receiver and place a phase modulated carrier at 2.5 times the guidepath frequency. The choice of two and a half times seemed to maximize the frequency difference between the signal and the guidepath harmonics. I seem to recall that experiments showed that we had about 100mV of signal at the central station receiver, but we wanted to allow for a worst case position (physical position of the tractor) where the signal was very much weaker. I believe that we had a particular value in mind for tests, but I do not recall what that was. That the communication actually worked in the real warehouse was, when it came to it, a more important test.

The task of designing a suitable receiver was a daunting one. It had to be made according to a robust plan, and that plan had to be executed intelligently with carefully chosen details.

I mapped out a plan for a double conversion receiver. I perceived that analogue filter design was a weakness in our team, (There was no spice, or filter design programs available for running on your pc in those days. There were no pc’s!) so I came up with a scheme that relied on filtering with anything so complicated as conjugation of poles, to an absolute minimum.

The block diagram of the receiver in a later form is shown here.

up-traffic-receiver

The plan was to use phase inversion keying (phase shift keying where the phase shift is 180 degrees). The source of carrier was a phase locked loop locked on to the guidance signal. The modulator was an exclusive OR gate.

I set up project nomenclature for frequency in which the guidepath frequency was nominated ONE frequency unit (“1U”) and the data carrier, 2.5U. The actual frequencies were 6.25kHz for the guidepath, and 15.625kHz for the carrier.

At the receiver, the first stage was a very simple high pass filter to boost the carrier to guidepath signal ratio. These have a ratio of frequencies of 2.5 which is about 1.3 octaves. Three zeros can give us (6dB per octave each) about 23 dB of preference of carrier over guidepath. For the analogue multiplier, I selected a Motorola part containing a Gilbert Cell (https://en.wikipedia.org/wiki/Gilbert_cell) (designed for use as an RF mixer) as an analogue multiplier to be the first mixer. The signal at the input to the first mixer could not be fed through a trigger, as there were expected to be more zero crossings due to the guidepath and its harmonics than from the carrier itself. The first local oscillator (LO) was at a frequency of 3U, giving an IF of 0.5U or 3.125kHz. The output from the first mixer was capacitively coupled to subsequent stages, giving a very satisfactory and very deep notch in the passband at zero frequency. Interfering signals from the third harmonic of the guidepath are at zero frequency here, so we get a lot of filtering out of a single capacitor just by carefully choosing the local oscillator frequency.

The next step in the block diagram is a bandpass filter utilizing a Riordan Gyrator. This was not part of the original concept plan and was not required according to my signal budgeting. After the gyrator, we really do have a signal that is stronger than the various interferences that we were planning for. This meant that the signal could be passed through a schmitt trigger. Interfering signals might alter the timing of the edges on the output of this, but (according to the budget) they would not alter it enough to introduce ambiguities in subsequent circuits.

The second Mixer was an exclusive OR gate. The output of this could have many glitches at the changes in state, and these were easily removed with a single pole low pass filter, and a second schmitt trigger.

The bloke who was assigned the task of putting this into effect had trouble and the task had to be rescued. Roger Riordan came to the rescue again. On this occasion, I did not give him freedom to do the task however he liked. I thought that I had too much investment in the planning of the topology, which seemed valid, even though the attempts to put it into practice had not borne fruit.

Roger wanted to change to an Analog Devices analogue multiplier, and I gave him free rein, even though the price seemed crippling (Forty five 1978 dollars, if I recall: AU$306 in 2016 money!), and he added the Riordan Gyrator to give a useful bandpass characteristic to the IF strip. Whereas we had been nervous of introducing active filters, this was no problem to Roger. After all, he had invented the Riordan Gyrator! At the time, I thought that this was adding an improvement that was not necessary, although we never conducted tests of the circuit without it. Recently when I have created a spice model (not a trick that was available to us in 1975) it looks as if the gyrator was necessary, so I must have made an error in my calculations at that time.

(Riordan Gyrator http://corybas.com/?ident=10W0G)

The receiver worked on the bench, and it worked in the warehouse when the transmitter was tuned, but it didn’t work when the tractor was out in the warehouse!

Some quick checks with an oscilloscope showed that the phase of the incoming carrier that represented a “1” (The MARK state) was different for each message. The challenge was to adjust the receiver to wide variations in reference phase. This is the matter that I suspect the different concrete formulations might have contributed to.

The microprocessor at the central station knew when a message was to come in, as the incoming messages were all in response to polling from the central station. The message format included a “front porch of a prolonged burst of carrier at the phase that represented the MARK state. The solution was to direct the signal at the end of the IF strip into a shift register that was clocked at eight times the IF frequency. At a time calculated to be about half way through the “front porch”, the shift register output was switched back to the input, making it into a ring counter. A ring counter that contained the last cycle of MARK phase signal. This was then used as the second Local Oscillator. For the rest of that particular message, whenever the phase of the signal was the phase that represented MARK, it was in phase with the output from the ring counter, and was 180 degrees out for a SPACE. This worked splendidly.

I added some (quite unnecessary) complication to remove a small phase shift caused by the quantization of the IF frequency cycle time. Not necessary, but it did no harm.

Only two of these receivers were made. Recently, I was sorting through some old stuff, and I found one of them! In this project, we made prototypes of many of the boards using a popular prototyping board that had gold edge connector finger at one end. We stuck to this format, so that when printed circuit boards were made, they were plug compatible with the prototypes.

img_1944-600-x-450

The flyback converter was to provide a minus rail for the multiplier. I think it might have run from plus and minus 12 volt supplies.

This board was found in a garage, and was covered with a thick layer of dirt and fluff. I only really wanted it to show here, so I washed it in the dish washer! Here is the rear view.

img_1945-600-x-450

The small board attached to the rear is the shift register/ring counter MARK phase regenerator. As you can see this was built up as a “one off” prototype board. There never was a case made to “do this properly”.

In the case of this receiver, it worked without a hitch. We couldn’t do bit error rate tests because we didn’t detect any bit errors.

When looked at with modern tools, the scheme holds up well.

I have broken the simulation circuit up to make it fit on this page a little better.

simulation-2

Here the signal on the guidepath is made up of the sum of The guidance signal of amplitude 15 volts, second harmonic of that at 0.5 volt, third harmonic at 1 volt (I am making it hard for the model, I don’t think the distortion of the guidance signal was really that bad!) and the modulated carrier with an amplitude of 50 mV.

simulation-3

The initial filtering “front end filter” of three zeros provides a preliminary reduction in the guidance signal. The arbitrary voltage source B1 represents the analogue multiplier. The first local oscillator V5 is at the third harmonic frequency. The LC tuned circuit plays the role of the Riordan Gyrator. The LT1017 comparator is used as a trigger (RF people might say “limiter”)

simulation-4

The arbitrary voltage generator B4 is set up as another multiplier, but it is only multiplying digital signals. It plays the role that was played by an EXCLUSIVE-OR gate in the real hardware.

Even 30 years later, I love the way the waveform of the data emerges in stages as we look at various points of the circuit. This was very exciting at the oscilloscope in 1978.

combo

Top Left: The guidance signal is so large that the data is completely invisible on it. Top Right:. Even a passive filter of three zeros give a very different view. Middle left: After the multiplier. The data is at 3.125 kHz, the second harmonic of the guidance signal is at 6.25 kHz, the third harmonic is now DC and the Remnant guidepath signal is now at 12.5kHz. Middle Right: After the gyrator. The lowest frequency we see here is our signal. Bottom Left: the trigger picks the signal out (at IF frequency). Bottom Right: The red trace is the “raw” data. Notice that it is low for most of the time to the left of the trace, “mucky” in the middle” and high for most of the time to the right of the trace. The blue line is the “cleaned up” data.

The data was ISO1177 format (for a UART) at 300 bits per second.

Unfortunately, the driverless tractor system that this receiver played a part in was short lived. This was not a reflection on the driverless system but the fact that the warehouse workforce was not ready to share their work space with an automated system. This is why the “piggy back” board on the back of the receiver was never laid out as a printed circuit board. There were many interesting aspects to this project, but the thread that links it to my next story is in the title “Two and a Half Times”. It is very easy with a phase locked loop to generate two waveforms that are locked together with a non-integer relationship between the frequencies. In this case, the key was to place a carrier so it could be picked up with synchronous demodulation but which was remote from the harmonics of a large interfering signal. In the next case, the application for the number “Two and a Half” was quite different, but there were common threads as you shall see.

Blog Post 39 TWO AND A HALF TIMES PART 1A

Posted 25-03-2016

HYTECO DRIVERLESS TRACTOR SYSTEM MODEMS
Driverless Tractor (900 x 495)

The Hyteco Driverless Tractor System was a scheme for running towing tractors around a circuit in a large warehouse. The tractors followed a guidepath which consisted of a wire set in the concrete floor. The wire carried a direct current with a 6.25 kHz sinusoid superimposed. The wire also carried other signals for communication purposes. The guidance system was an adaptation of a proprietary system that Hyteco had the agency for. Indeed, part of the justification for the development of the system was to sell more guidance equipment. The system had many interesting aspects to it. One of these was the provision for communications between the tractors and the central controller. Each tractor and the Controller had a central processor which consisted of a Motorola “D2Kit” which used a 6800 processor. This was 1978.

We had a “DECwriter” Printer/keyboard terminal which had a fixed speed serial port at 300 bits per second. I made a decision very early in the project that the system communications would all be ISO1177 style (UART Compatible – Start/Stop serial) so that the DECwriter could be used for sending or receiving test messages. Indeed I remember at one time a tractor with the DecWriter mounted on it was charging up the factory with a bevy of blokes running along behind feeding out the extension cord which was powering the DECwriter which was printing out “The Quick Brown Fox Jumps over the Lazy Dog” or something like that.

We had communication from the Controller to the tractor in a realistic environment, and we could prove it!

The decision to format the data stream in this way thus had an advantage (for exercising, proving and testing), but it also caused us some problems. In some places in the system, we had to derive a bit clock from the guidance signal, and that was possible, but in the technology of the day, it took quite a number of CMOS SSI integrated circuits.

ISO 1177 data is not always a good choice where signal to noise (and consequently non-zero bit error rates) is an issue. A UART only has to mis-read one START BIT, and probably the whole of the rest of the message is lost. Nevertheless, this was an early decision (as it had to be) and we were stuck with it and we stuck to it.

There were four distinct communications paths in this system.

1. Location Loops

One was communication to tractors from particular places so that the tractor had location information. This might have been seen as a design challenge, but it was one of those things that worked first time and never gave any trouble. The scheme was to provide an auxiliary guide path signal which was phase-reverse keyed. the demodulator required no more than a schmitt trigger on the guidepath signal and the auxiliary signal, an exclusive OR gate and a low pass filter. Maybe there was a third schmitt trigger at the end, but the result was a channel that was trouble free when fed directly to a UART.
Location Loop marked up (900 x 645)Location Loop – set in the concrete floor, and connected to a box attached to a nearby wall. The box contains electronics that imposes a data byte on the loop by reversing the current in the loop. The two coils shown are mounted on a passing tractor.
Location Loop ReceiverBlock Diagram of Tractor mounted Location Loop decoder. Unequal delay in the Guidepath and Loop sensing circuits can lead to glitches and multiple edges on a change of logic state. the duration of these is very short compared to a bit period, enabling the very simple RC and trigger clean-up circuit to be used.

2. Turnouts

There were small circuit boards in lineside boxes that switched the guidepath current from one wire to another, and thus provided the function of a “turnout” or “pair of points”. The receive end of the communication to these from the central control was designed by a bloke named Peter Resmer, who made a good job of it. Like the location loop circuit, it was one of the aspects of the project that fell into place quickly and didn’t need constant revisiting.

Each of the other two communication paths was much more troublesome. These were Communication from the Central controller to the Tractors, which we called the “Down” direction, and communication from the tractor to the central controller which we called “Up” traffic. (One needs terms, and we chose these from railway practice. Our system was a railway system in every respect but one: it didn’t have rails.)

3. The Down Channel Communication from the Central controller to the Tractors

This was tackled first. There were several factors at play in determining the choices here. We were a bunch of young, inexperienced engineers and technicians. We were supposed to be designing a practical system: not making world shattering advances in the technology of the components. Any established designs that could be brought into play with minimum mucking around looked good. This was the early days of telephone line modems. Frequency shift keying was very popular, and there were many ICs available. Most of the data sheets had beaut looking circuits in the applications section. I was a bit naive about how reliable application notes circuits are in those days. We decided to use frequency shift keying an adapt a data book application circuit to suit our need.

The story of how we encountered problems and learned a lot and got this to work is a story in itself. We got it to work, but there had been troubles, and I didn’t want to launch into another troublesome task. Added to this was the fact that for the Down Channel, we could transmit a strong signal. The signal was added to the guidepath signal, and the only upper limit to the data signal power was the power at which it interfered with the guidance system.

In this respect, the Up signal path was completely different. The tractor ran on a concrete floor with the guidepath wire set in it. It was required that the tractor had about 100 mm clearance, so however the tractor was to convey the signal into the wire, it was most unlikely to be a high powered signal when established in the wire.

Whenever a communication system is asymmetrical in that one station communicates with the others, but that they don’t communicate with each other, then the optimum focus for investment is also asymmetrical. A broadcast transmitter working with a large number of receivers is the classic case. If improvements to the system can be applied at the transmitter, then they have to be applied only once. The result is that we have large powerful expensive broadcast transmitters, and large numbers of cheap, possibly not very sensitive or selective receivers. The same asymmetry rule applies whatever the direction of the traffic. The equipment in a cellular mobile phone base station will be vastly more expensive than any individual phone, but might not be vastly more expansive than the population of phones that it serves. There were no mobile phones in 1978, but this point was clear: The central controller circuit could be complex, but the tractor circuit should be simple and cheap.

The tractor transmit antenna was designed by Roger Riordan. I have described this in this blog before (“Time Passes 1” posted in August 2013. You can find it easily by placing “Riordan” in the search box.). It happens that that transmit antenna design does not have the bandwidth to carry the FSK type of signal used for the Up traffic.

I had been concerned about bandwidth for a completely different reason. The receiver had to pick out a small signal from a channel with other large signals on it. One aspect of our efforts to find the signal in amongst all the noise was to place the signal in a quiet place in the frequency spectrum, and use no more bandwidth than necessary. The FSK encoding used for the Down traffic had to use much more bandwidth than the theoretical minimum, as the characteristic relationship between frequency and voltage at the phase locked loop chip VCOs, and the need for voltage swing dictated a large difference between the frequencies representing mark and Space. A different scheme was called for.

When the signal is weak, and of narrow band, it become important to synchronize the transmitter and the receiver. The scheme chosen was to use frequency sythesizers clocked from the guidepath signal at the Tractor and at the receiver and place a phase modulated carrier at 2.5 times the guidepath frequency. The choice of two and a half times seemed to maximize the frequency difference between the signal and the guidepath harmonics. There were other advantages as well, which I will go into next time.

Blog Post 38 Class C with Immediate Feedback

The story so far…

I have postulated that for high efficiency, one needs to drive a tank circuit in one of two ways: with a current drive,

Tuned Circuit Current drive

or with a voltage drive:

Tuned Circuit with Voltage drive

It had not escaped my notice that traditional Class C stages did neither of these. Since posting those musings, information has come my way about how real Class C stages really did it, and I will pass that information on in a later post. For now, I continue to use the second of these.

I have investigated the introduction of amplitude modulation by pulse width modulation. Unfortunately, there is not a linear relationship between pulse width and amplitude of the ringing of the tank circuit, and I have introduced two schemes to overcome this non linearity. The first was negative feedback around the modulator and a following demodulator. Modelling showed that this could, in principle, give good results. I have since been informed that negative feedback around an amplitude modulated transmitter is a trick that has been used in practice.

The second scheme was a pulse width modulator that did not give pulse width proportional to instantaneous baseband voltage, but contrived a pulse width that would give the desired amplitude at the tank circuit. This gave good results as well.

I can see no reason why if a really high fidelity amplitude modulator was required then both of these techniques could not be used.

However a third technique has arisen. It is simpler than the other two. Maybe it could stand on its own in a low fidelity speech band modulator, or in combination with feedback around a demodulator for a higher fidelity application.

In developing the explanation of this third technique, I will not follow the path that led to its accidental discovery. However, by way of confession, I will tell you about the discovery.

When I was spice modelling the feedback around the modulator – demodulator combination, I was troubled by a crazy wobble that arose in the waveforms. For a while I thought that I had discovered a circuit instability that was being exposed by the LTspice, and I explored a few ways to deal with it. Soon it became evident that it was an artifact of the LTspice itself, and was completely cured by reducing the Maximum Step Time. I had learned a valuable lesson about setting up spice parameters, but more than that, I discovered that one of my attempts to quell the instability had revealed itself as a really valuable trick.

This “design by serendipity” is an interesting phenomenon: not to be dismissed as one of the paths to good design ideas. This is a discussion for another time.

My initial pulse width modulator scheme was very simple. The carrier was generated as a triangle waveform. This was added to the baseband signal, and the sum offered to a threshold detector. The instantaneous value of the baseband determined how far up the triangle the threshold detector threshold was, and thus the width of the pulse.

In Post number 35, I reduced the carrier to 5 kHz so that it and a 1 kHz sinusoidal baseband signal could both be clearly seen on the same axes, and presented a graph to explain this modulator action.

I reproduce it here.

Demo waveforms

The next important detail in the explanation of this scheme, is the time or phase relationship between the excitation pulse and the voltage waveform at the tank circuit. I had shown this relationship in Post 37, and I reproduce that here as well:

1 Tank waveform

The voltage on the tank circuit lags the fundamental component of the pulse waveform by 90 degrees.

If we place an RC circuit with a break frequency that is much lower then the carrier, on the Tank, that will give a further ninety degrees lag. Overall, 180 degrees lag, or a suitable signal for negative feedback. Alternatively (and this is what I have done below) we can set up the RC to give about 90 degrees lead, which gives us an output that is in phase with the excitation, and then subtract this from the modulated carrier. Here is my circuit model:

Pic38-05

The tank circuit is made up of L1 and C1. The resistor R1 represents the load (antenna if this is a transmitter). C2 and R16 are my lead network. They provide a feedback sinusoid at the carrier frequency and in phase with the excitation.

V1 is the carrier generator, which is of a triangle waveform at 1 MHz.

V3 is the baseband signal. In this case, it is a triangle waveform as well. I had developed the habit of doing this, as it is very easy to visualize the distortion if there is any curvature of the reproduction of the ramps in a triangle base band signal. I will quickly go through the way my model represents a pulse width modulated drive for the tank circuit. A comparator is represented by the switch model, which is closed for positive voltage on the differential inputs and open otherwise. V2 and R2 convert the switch state to a voltage waveform, and this is presented to the tank circuit by the voltage controlled voltage source E1 (which represents the power stage). As before, the pulse width modulation is executed by just adding the baseband to the sawtooth carrier. The switch/comparator converts this to a pulse width modulated signal as the base band shifts the carrier sawtooth up and down and varies the time during which it presents a positive value to the switch/comparator.

It will be seen that the switch is closed by a positive voltage, but that closed switch gives the negative state to the output drive. Thus the switch – voltage follower combination is inverting to the carrier signal. The feedback from the lead network is fed to the plus input to the switch differential input is thus negative feedback.

This circuit is the same as in previous postings except for the lead network and the application of this negative feedback to the modulator.

Here are the revealing traces.

Pic38-06

The red trace is the output from the power stage (voltage controlled voltage source).

The brown trace is the voltage on the tank circuit (output of the transmitter).

The blue trace is the feedback signal derived from the lead network.

It can be seen that as the base band signal applies a bias to the triangle carrier to provide a wider part of the triangle to the switch, and to broaden the pulse, the feedback will apply an opposite bias and tend to make the pulse narrower – that is reduce the drive to the tank.

The result is shown below. The blue trace is the base band signal. The brown is the output from a synchronous demodulator. The thickness of the brown line represents carrier feed through. Notice that the brown line is “thicker” when the voltage is high: that is when the carrier amplitude is highest.

Pic38-07

There IS some distortion visible. The brown line is seen to be slightly curved when shown in close proximity to the baseband signal. Note that I have used the circuit exactly as it was when I was trying to eliminate what I thought at the time to be an instability. I have not explored how much negative feedback can be applied here. When you consider that this negative feedback has been applied at a total cost of one capacitor and one resistor, it is seen to be a cost-effective result. It would most probably be worth incorporating in conjunction with overall feedback around a demodulator. I will leave this as an exercise for the interested reader.

This “Class C” business has gone on for longer than I had originally planned – and it is still yielding interesting material. I will leave it for a while now, and come back to it later.

37 Class C Part 4 Focussed Modulator Design

The story so far:

After proposing pulse width modulation of the input signal of a Class C stage to determine the amplitude on the output, I showed that if we used a simple pulse width modulator that varied the pulse width in proportion to the instantaneous value of the baseband signal voltage, we got a distorted result.

I postulated two approaches to fixing this in Post 35. The first was negative feedback and the second was “smarter modulator”. I showed how effective feedback can be in Post 36. Now we turn to the “smarter modulator”.

The short version is that the output (in real life – high powered) tank circuit is mimiced with a low voltage LC circuit. This circuit is fed with a variable width pulse to maintain the amplitude close to that of a reference signal obtained by amplitude modulating a representation of the carrier with an analogue multiplier.

I will provide particulars and then show the result.

Particulars

There are two steps.

First, the carrier signal is processed to generate various special signals that are required by the modulator proper.

It will be easier to find what follows clear if it is remembered that the tank circuit has the property that the quasi sinusoidal on it is placed so that the driving pulse falls on the positive going zero crossing.

1 Tank waveform

The first signal generated is a signal I call “dual_slope”.

The signal has a notch shape that is centred on the positive going zero crossing of the carrier.

2 Dual_Slope

This could be generated in any number of ways. If you are interested, this is how I did it.

3 Timing triangle generator

The second is a pulse “Sample” that occurs during the time when the carrier is near the most negative value. This pulse is accurately centred on the time when the carrier is at exactly the minimum value. See the blue trace below. The third is a pulse of less critical timing “Clear” that occurs later.

4 Sample and Clear

As before, I won’t go into the details of how these pulses are generated, but will show my model schematic for those interested.

5 Sample and Clear generation

The only other signal required for the modulator is a representation of the amplitude modulated signal that the Class C stage is to produce. Of course in this low level signal modulator board, this is easy to do with an analogue multiplier IC.

6 Analogue multiplier modulated carrier

Second Step
Now we come to the actual Pulse Width Modulator for Low distortion Class C stage.

7 Modulator

It is easiest to describe the operation of this when it is already running. It is easy enough to extend this to graceful start-up. I will leave that to the imagination of the reader.

To the right of the circuit diagram there is a tank circuit and an exciter arranged just as I have arranged these in previous Class C stage models. The idea here is that these are all small signal components on the “modulator board”. It has appeared later that there might not be any reason for this “Mock Tank Exciter” and “Mock Tank”, as the actual exciter and tank could play the role here. I will leave this as it is for this explanation.

The voltage on the Mock Tank is compared with the modulated signal from the analogue multiplier at the voltage controlled current source G3. This then provides a current that is proportional to the difference. This current is shunted away by diode D1 or diode D2 except when the voltage controlled switch S11 is closed during the “Sample” time.

8 Modulator waveforms

The voltage on the Mock Tank circuit is the brown trace. The reference modulated carrier is the blue trace. It will be seen that the magnitude of the reference modulated carrier is greater at the negative excursion. During the Sample time (red trace) the current representing the difference is used to charge capacitor C6. At the end of the Sample pulse, the charge on C6 represents how much the Mock Tank circuit is falling behind the reference signal. This is then used to determine the duration of the pulse of energy imposed on the tank by the exciter in the following cycle. C6 is discharged on the Clear pulse (not shown) The voltage on C6 is converted to a width of a pulse that is properly centred so as not to introduce phase modulation by comparing it with the dual_slope signal.

9 Pulse width modulation

Here the DS_Offset (Which is “dual_slope” with an offset added) is shown in brown. The voltage on the capacitor C6 is green as before. The blue trace shows the excitation signal for the Mock Tank. It is high whenever the C6 voltage is higher than the voltage of “dual slope”. It can be seen that this scheme will provide a variable pulse width to excite the tank, and that the width will vary as required to provide just enough energy to the Mock tank to have its voltage fall just a little behind that of the reference signal. At the same time, the driving pulse is properly timed so that there will be no phase variation as the amplitude is modulated.

I am writing this up many weeks after I developed the model. There are various reasons for regarding this as unnecessarily complicated. The complication would all be accounted for in a very small board area of small signal circuitry, so would be readily born if it gave the best result. What result does it give?

10 input vs demod

The red trace is the base band signal at the very input to the model.

The brown trace is (with attenuation and offset) the output of a synchronous demodulator on the high powered tank circuit.

One way to check for linearity is to modulate with a slow ramp and look for the straightness of the ramp on the output. here is what we get.

11_sawtooth that is better

The brown trace is the input to the modulator, and the blue trace is an attenuated version of the output from the demodulator. That is linear!

Compare this with my initial “crude” pulse width modulator in which the pulse width is proportional to the voltage.

12

36 Class C Part 3

36 Class C Part 3 Feedback around Modulator

The story so far:

I have investigated the idea of a “Class C” amplifier and pushed the notion that the feature that the active device conducts for less than half the cycle is not definitive. It seems much more important to dwell on the high efficiency amplification without regard to distortion, and then recovery of the wave shape afterwards. In AM or CW transmitter service, the recovery is carried out by a high Q tuned circuit called the “Tank Circuit.”

Although possibly not available to “old time” circuit designers, the idea that a high efficiency active device that is working as a switch, could be modulated with pulse width modulation seems attractive. Unfortunately a very simple modulator that gives pulse width proportional to signal gives a distorted amplitude modulation envelope.

Here is the waveform that I obtained when I modelled a circuit consisting of these stages:

1. Pulse width modulator
2. Switching Power Stage
3. Tank Circuit
4. Diode demodulator.
Pulse width modulated sine simple waveform

The brown trace is the modulating waveform, and the blue trace is the output from the demodulator. Note that the blue trace is much “broader” on the positive excursions than on the negative ones.

See my Post “35 Class C part 2”.

It was evident that the simple law chosen for the modulator was not right for the characteristic of the tank circuit in changing pulse width back into sine wave amplitude. I suggested two remedies. The first, was to put negative feedback around the whole modulator – power amplifier – demodulator system: the second was to design a pulse width modulator that varied the pulse in a way that would give the correct result at the Tank Circuit.

Today’s post is to explore the first: Negative Feedback.

Here is my model circuit:

Feedback diode circuit

The demodulator is the diode demodulator we saw in the last post. I mentioned then that I added L2 in series with C2 to make a trap as I wanted to reduce the carrier, but did not want to put filter poles where they would interfere with my feedback loop. Notice the resistive divider R3, R4. This reduces the asymmetry that one gets if a shunt capacitor is placed directly on the cathode of the diode. In such a case, the diode charges the capacitor quickly, but it will discharge much more slowly. In this circuit, C3 and C2 are charged and discharged with much more similar resistances.

That’s the logic of it anyway. Probably completely invalidated with the addition of the series LC trap. Maybe diode demodulators is a subject for another day.

The resistive divider on the Modulation signal giving the signal Modbuf is just there so that we can see an input signal and an output signal that are similarly scaled.

Here are the traces.

Feedback diode modulator traces

It is easy to see that the output signal is very much less distorted than without the feedback. As the output waveform is not created with a continuous process (the pulse width modulation), I cannot simply run a spice FFT on the output to measure.

I calculated the phase shift of the base band signal as it found its way along the forward path. The actual amplitude modulation of the carrier at the tank circuit is lagging the modulating signal by about 2.2 degrees. The output of the demodulator is lagging the modulating signal by 30 degrees.

I tried substituting a synchronous peak detector for the diode detector. This effectively gave me a sample and hold on the peaks of the full wave rectified modulated waveform. This gave me a minimum ripple and enabled me to reduce the low pass filtering required for a smooth baseband signal. The result is shown below. You will see that the brown trace (output of demodulator) lags behind the blue trace (modulating signal) very much less with the synchronous demodulator.

sync demod

35 Class C Part 2

In “Class C part 1”, I wrote about a discussion I had had with the designer of a low powered AM broadcast transmitter. That was Brian Cabina, who I had met through the Music Broadcasting Society. Must have been in the early 1970s. By the time that society began transmitting, the FM band had become available, but during early planning, it was proposed to utilize the AM band. New frequency allocations were being opened up (One was taken up by 3CR, for instance), and it had been hoped to grab one of these.

He had told me that with an amplitude modulated Class C transmitter, one had to put the modulator on the output of the last stage “because with Class C there is too much distortion”.

AM Transmitter with modulation of the power to the Class C output stage
AM Transmitter - High Power Modulator

There is a heavy price to pay, as a portion of the power for the RF power amplifier has to be provided by an audio amplifier. This was expensive power, both in terms of capital cost, and in terms of efficiency.

I suggested that the blanket statement “with Class C there is too much distortion” is nonsense, and asked the rhetorical question “Can I justify that”?

My justification is that there are two completely independent avenues for distortion in a Class C transmitter and to blur the distinction between them, by grouping them under the heading “the distortion” is to prevent precise discussion.

Here are the two distinct distortions defined in a way that in my mind are clearly distinct.

Distortion 1.
This is distortion of the RF carrier in the Class C amplifying device. This distortion is removed (more or less) by the filter on the output. In traditional AM transmitter (or CW transmitter, for that matter) practice, the filter takes (took) the form of an L-C tuned circuit called the “Tank Circuit”.

Distortion 2.
This is the distortion that would be introduced in the audio channel between the input to a small-signal modulator on the input to the Class C stage, and the audio channel as it appears in the form of amplitude modulation on the output.

Distortion 1 is generally gross distortion indeed, and if that magnitude of distortion were to appear as Distortion 2, then that would certainly disqualify the circuit for serious AM work. However, Distortion 2 is either not related at all to Distortion 1, or related so loosely, that we can address Distortion 2 without regard to Distortion 1 at all.

If we were to modulate the signal at the input to a Class C stage, so as to achieve linear amplitude modulation of the output carrier, then what form should that modulation take? Not amplitude modulation. The Class C stage earns its stripes for efficiency by behaving as much like a switch as possible. The active device is either “on” and exhibiting as low a resistance as possible, or it is “off” and (in the instant) looking like an open circuit at the output. An exception that is possible, but divergent from traditional practice is that either one output device is “on” or another is, so between them a low resistance is presented to the output at all times. (See “Tuned Circuit with Voltage Drive” in the last Post “34 Class C Part 1.)

This is much more obvious to us these days now that we are familiar with switched mode power supplies, than it was to many armchair philosophers who contemplated Class C circuits in years past.

AM Transmitter - Low level Modulation

AM Transmitter with Low level modulator that modulates the signal to the Class C Stage

Our driver circuit modulator must maintain the signal amplitude to maintain the output stage efficiency. This leaves only one choice, the modulator must be a pulse width modulator.

This raises two questions.

Question 1.
If our transmitter block diagram has a small signal pulse width modulator followed by a Class C stage, is it possible in principle to provide an overall low distortion path to the audio.

Question 2.
What are the implications for the Class C stage of driving it with a signal of varying pulse width?

Let us go back a bit…
The tuned Circuit with voltage drive that I suggested in the last post was not really practical in “valve days” as the tuned circuit circulating current all passes through an active device. Any tuned circuit that was pitched at such a high impedance that the on resistance of a valve would not impose too much damping, would have much too much voltage swing for the valve to survive.

The huge differences between the old and new technologies are so obvious, that we don’t often bother to put numbers to them. Let us do just that in this case.

A 6V6 beam Power tetrode has a peak anode volts rating of 1200 volts, and a maximum anode current of 105 mA . The data sheets did not cite an equivalent of “RDSon”, but I estimated this graphically in the last post as 232 ohms.

An IXTP3N120 N channel MOSFET available at the one off price of AUS$13.461 from Element 14 has a maximum drain current of 3A and an RDSon of 4.5ohm. To get this low on resistance with 6V6s, we would have to have 52 of them in parallel. The change from one technology to another has not just made a change of degree in some parameters, it has of course made a change that has made completely new circuit arrangements available to us. This is blindingly obvious when we think about circuits such as switched mode power supplies, but it applies to Class C,   RF power amplifiers as well.

These days we might search in a particular area of our “concept space” for a high efficiency design, and find a good result. That very same area was disqualified in the “valve days” on the grounds of heater dissipation alone. (The heaters in 52 6V6s dissipate 147 watts) In the real world 21stcentury, we might choose a different voltage range (lower), a different current range (higher) and a different value for “on” resistance of the active device(s). We choose these on their merits, rather then matching the performance of a huge number of 6V6s in parallel.

A Class C stage, which you might remember, is characterized by me (if not by the rest of the world) as one in which the (an) active device “is driven so as to provide a switching type of waveform without regard to distortion, and then the signal is recovered from the harmonics by a high Q tuned circuit called the Tank Circuit.”. Such a stage can be built around what I called the “Tuned Circuit with Voltage Drive” in the last post. Here is the model circuit again as a reminder.

Tuned Circuit with Voltage drive

In this (what an old colleague of mine would call a) circuit topology, the circulating current in the tank circuit all passes through the active device(s) in the voltage source. Internal resistance in the active device(s) will be in series with the L and C. This is only practical if the internal resistances are very low. This is the case with (for example) MOSFETs with a circuit like that in a switched mode “half bridge”.

Model of Voltage source for Tuned Circuit with Voltage drive

Here is an amplifying stage put together along these lines.

Tuned Circuit with Voltage drive hoo

We start off with a source of signal at the carrier frequency. This is squared up with a trigger (which the RF boys (and girls) would call a limiter(?)) which I have implemented with a spice switch element. This converts the signal into a train of pulses which drive a complementary pair

The spice switch model has an “On Resistance” parameter, which I have set to 0.1 ohm. This accounts for the distorted nature of the waveform at the output of the power stage. This output has to carry the large sinusoidal current in the Tank Circuit.

The very output, the voltage imposed on the load resistor R1, is a sinusoid with low distortion, which we might regard as a recreation of the waveform on the input to the amplifier.

This “topology” which one might regard as an implementation of the “Tuned Circuit with Voltage Drive” ideal, will appear in several examples to follow.

MY definition of “Class C” includes the concept “ without regard to distortion”, and this is embodied here. The signal for exciting the Tank circuit becomes a train of pulses, and then is returned to a sinusoidal form by the Tank Circuit itself. Is this the distortion that I was warned about when I was a youngster? It is what I defined as Distortion 1. above?

What are the implications for Distortion 2 (the distortion of the modulating signal) of my practical implementation of “Tuned Circuit with Voltage Drive” topology?

Let us investigate this.

There are really only two ways we can apply modulation to the train of pulses at the output of the limiter. One is to modulate the amplitude of the pulses, and the other is to modulate the width of them. A moment’s thought will reveal that the modulation of the amplitude of them, amounts to the varying of the voltage source V1 in my circuit model above. This is the ordinary old modulation at the output of the RF amplifying stage, with the attendant disadvantage that some of the power to the output stage has had to come from an audio amplifier and is expensive power.

Pulse width Modulation of the Drive to a Class C Output Stage

Here is my first crack at a model to demonstrate this:

Pulse width modulated sine simple circuit

The pulse width modulator is set up to modulate the carrier with a 1 kHz sine wave. This is done very simply by adding the modulating sine wave to a triangle wave at carrier frequency and then passing the sum to a zero crossing detector. I have demonstrated this with the waveforms below in which I have reduced the carrier frequency to 5 kHz so that the carrier waveform and the modulating waveform can both be seen clearly on the same axes.

Demo waveforms

Here the blue line is the base band signal. The brown trace is the blue line with a triangle at the carrier frequency added to it. The triangle has the same slewing rate on the positive and negative going slopes. The red trace is the output of the zero crossing detector. This arrangement of pulse width modulator has pulses that are centred in a periodic fashion. That is the fundamental of the fourier series does not have phase jitter. This pulse width modulator has pulses with a width proportional to the voltage of the baseband signal. Is that the right characteristic in this case?

In this model, I have represented the power output active devices as a spice model voltage follower. You will understand that the circuit models that I present here have been placed in an order that has, I hope, a logical pattern to it. This is by no means the order in which the models were created. During the evolution of each model, there have been several steps that we will not bother with here. It just means that changes crop up from model to model. Generally, I won’t comment on these if they have no impact on the argument.

A simple diode demodulator is used. The introduction of L2 in series with what had been a low pass capacitor C2 to make it into a trap, had been done at some stage to reduce the carrier ripple on the output. I wanted a clean recovery of the baseband signal without placing a pole too low. This was my quick “no thinking” solution, which suited me in the moment better than a multi-pole filter.

Here is the base band modulating signal and the output on the same axes.

Pulse width modulated sine simple waveform

The brown trace is the modulating signal, and the blue trace is the output of the demodulator. Considerable even-order distortion is evident. Is this the distortion that I was warned about all those years ago, that I have identified as Distortion 2?

It can possibly be seen more clearly if the base band signal is replaced with a linear ramp.

Ramp

Here the modulating signal is a trapezoidal wave of low frequency. Here we look only at the rising edge (brown trace). The blue trace is the output of the demodulator.

If this is Distortion 2. then it seems pretty benign to me, and aught to be amenable to a little fixing with negative feedback.

Then again, and this is a possible second approach, maybe the “pulse width proportional to voltage” is not the correct transfer function for the pulse width modulator in this application. Maybe a modulator designed with a little more care would fix this distortion.

These two approaches – negative feedback, and smarter modulator – will be examined in the next post.

By the way, I am aware that conventional Class C circuits are not amenable to pulse width modulation. I suspect that the tank Circuit would have to be re-tuned every time the pulse width was changed.

Here is a “modern” (solid state) schematic for a Class C transmitter that I found on the internet.

1W_RF_Amplifier

Aren’t RF designers funny people! It seems that the active power device is also performing the role of limiter (approximation to zero crossing detector). I interpret the FD700 diode between base and emitter as being to provide a symmetrical non-linear load for C1 so that the transistor can be driven hard on positive excursions. Why don’t RF designers have to worry about transistor saturation? You can see that the reactance of the RFC is in with the Tank circuit when the transistor is “off”, but not when it is “on”. This circuit could not be used with pulse width modulation as the Tank Circuit tuning would be adversely affected.

34 Class C Part 1

Foreword

This post has been delayed, not through any problem getting the content together, but by problems presenting the content on the BLOG page. My good friend Andrew Beal has been helping me with those problems.  They are not all solved yet, but I am publishing this now (19-04-2015) as I am concerned that what is actually posted has fallen too far behind with thinking out material for this blog. As I attain more mastery over my formatting problems, I will come back and knock this post into better shape. And now, to the post…

Class C Part 1.

It used to be that much was made of the division of the bias arrangements for active devices into three classes. Class A, Class B and Class C. Some feature had to be found to easily distinguish these. The feature that was usually used was the proportion of a signal waveform for which the active device was conducting. This was expressed in degrees. Thus it was said that a Class A stage conducted for 360 degrees of the waveform, a Class B stage conducted for 180 degrees of the waveform, and a Class C stage conducted for less than 180 degrees of the waveform. In the case of vacuum tubes, there were many divisions between these. Thus we had push pull amplifiers classed as AB1, AB2 etc. It all depended on how one contrived to pass the amplifying task from one active device to the other at the zero crossing. These “intermediate classes” are explained in detail in The Radiotron Designers’ Handbook  Chapter 13 Sections 1 and 7 (1).

It has been shown by Douglas Self (2) that when junction transistors are used as the active devices, there is no advantage in attempting to find an optimum with a compromize between the classes, and it is best if a linear amplifier is required, to commit to either Class A or Class B. An optimum design of a Class B stage has such a small output device quiescent current that it doesn’t warrant any subscripts after the B.

I have never designed a Class B MOSFET amplifier, but I have been reliably informed by one who has, that there is a particular trick. MOSFETs do not suddenly snap from their linear operation value of gm to zero as they pinch off, but go through a gradual transition. In an amplifier with  a push pull complementary pair of Class B MOSFETs they are biased so that with zero signal, both output MOSFETs are sitting on their transition between linear operation and “off” so that each is exhibiting  a gm value of half that for linear operation. At this point, they are both conducting (a little) and contributing half of the combined gm each.

As I see it, the number of degrees of the sine wave cycle is not really a definitive measure. All we can say is that active devices are set up to take half the signal each: one takes the positive half waveforms, and the other the negative half waveforms. Class B amplifiers have an efficiency advantage, partly because they exploit very particular properties of an audio signal.

An audio signal:
(a) Hovers about zero and deviates from this in both polarities in a more or less symmetrical pattern.
(b) Has a wide dynamic range. This means that an amplifier that has to meet some particular maximum power requirement will spend a lot of time delivering much lower output power.

Class C.

This is traditionally defined as an amplifier design style in which the active device is conducting for less than 180 degrees of the waveform cycle. This class evolved in a very particular application: the power amplifier for a radio transmitter. This application also has some very restrictive features the key one being that the bandwidth of the signal is small compared with the centre frequency.

This means that the amplification stage can be designed with an eye to maximum efficiency and very little (or none at all)   effort to minimize distortion. The waveform distortion can then be reduced by a tuned circuit at the output. The tuned circuit that does this waveform restoration is called the “Tank Circuit”. I wonder how that term originated. (The expression “Tank Circuit” does not appear in my hard copy OED. It is to be found at http://www.merriam-webster.com/dictionary/tank%20circuit but without attribution.)

It seems that it is relatively easy to build a tuned circuit that has a high enough Q to make a practical approximation to a sine wave when being driven by a non-sinusoidal periodic waveform, and yet a low enough Q to accommodate the sidebands when amplitude modulation is applied. After all, the second harmonic of the carrier is usually a lot further away than the upper sideband.

There is even an opportunity to exploit the steeply falling spectrum of most audio material. This makes it possible to boost the high frequency end whilst making very little increase in the peak value of the composite waveform. This means that it would be possible to choose a Q for the tank circuit that is so high that the extremes of the sidebands are attenuated, but then compensate for this with pre-emphasis in the audio channel before the modulator. This would be a very minor step compared with the spectoral shaping, dynamic range reduction (compressing and limiting) and peak to RMS ratio reduction jiggery pokery that routinely goes on in AM transmitters.

It is always possible to add low pass filtering to further reduce the harmonics introduced in the Class C stage, and perhaps the “pi coupler” used for impedance matching, provides some low pass filtering at no extra cost.

Once freed of the requirement for linearity, and with a focus on high efficiency, we need an active device that acts like a switch. It is either a zero ohm conductor, or an open circuit, and it does not dally about wasting energy in some intermediate state. This sort of requirement is very familiar to us in these days of solid state devices and switched mode power supplies. It might have been obvious in the days of yore, but with thermionic devices, this was an ideal that must have seemed very remote.  Designers had to make do with what they had.

There are two complementary ways we can add energy to the tuned tank circuit without interfering with its tuning or severely lowering its Q. One is to introduce a periodic waveform voltage in series with the L and C, and the other is to introduce a periodic current waveform to the parallel tuned circuit.
Tuned Circuit with Voltage drive
Tuned Circuit with Voltage Drive

Tuned Circuit Current drive
Tuned Circuit with Current Drive

The scheme of driving the tuned circuit with a current is the scheme used in linear rf amplifiers in receivers, of course, where the high resistance of a pentode anode, collector or drain approximates the current source. The use of current drive is much more difficult in an environment where high efficiency is required. I have experimented (in simulation) with a circuit where a switched current is derived from an inductor. It came out as a circuit of a boost regulator, but with a tuned circuit instead of a reservoir capacitor on the output. Both switches have to be active switches (can’t use a diode for one of them as in a conventional boost stage), but the biggest problem is that the inductor that provides the current to the tank circuit, also detunes it. This could be corrected for, but only in a circuit where the duty cycle is fixed.

The one thing, we cannot do to provide energy to the Tank Circuit is to periodically connect it to a voltage source via a resistor. One would think that if the resistor value were low enough to transfer energy effectively into the tank circuit, then it would be low enough to lower the Q.

Yet, this is exactly what a traditional Class C output stage does.
Triode in Class C
Triode in Class C

Sometimes a pentode is used, but the higher dynamic plate resistance is of no use here. When the valve is conducting, it is “hard on”. The high resistance available from the pentode when biased in the linear region is not available. One supposes that the lower Miller capacitance of the pentode might be a benefit. (And Possibly lower “On resistance” – see below.)

So the valve is used in a very unsuitable way, but possibly in the only way that was available given the characteristics of valves. When a valve is used as the active device, the characterizing feature of “conducting for less than 180 degrees of the waveform” arises. Here is a model circuit that I have used to investigate the effect of varying conduction angle.
Duty cycle model complete small

This is a bit much to take in as (unfortunately) my crude circuit drawing graphics capability makes for bad presentation of much data in the available width. I will quickly run through this model a section at a time.
Duty cycle model 1 signal generation
This very uninformative circuit segment will become clear when I explain it. V2 is a voltage generator that provides the 1 Megahertz signal as a triangle wave. V3 imposes a ramp. The combined effect is a triangle wave with a slowly increasing offset. To a following circuit that is sensitive only to whether the result is positive or negative, the result is a pulse train at 1 MHz that varies from zero to 50% duty cycle.
Duty Cycle model 2 supply and valveThis part represents the supply and the valve. The voltage controlled switch is set up to vary with the control voltage in such a way that it reproduces the pulse train as described above. The 100 ohm resistor R2 and the two supplies V1 and V4 turn this into a pulse train that is at 5 volts during what we are representing as the “on” time, and minus 8 volts otherwise. The minus 8 volt supply is not part of the valve modelling, but is required to make the rest of my model work. It stops the ideal diode D1 from conducting during the “off” time. R1 represents the valve “on” resistance. You will observe that none of the voltages or resistances in my model have realistic values. I worked on this model until it worked. I have not spent further time rescaling it.
Duty cycle model 3 Tank CircuitHere is the Tank Circuit and the load.

The final part is that which measures the efficiency.
Duty cycle model 4 Measurement

The arbitrary behavioural voltage source B1 has an output voltage that is the product of the valve current and voltage. It thus represents the instantaneous power being provided by the power supply of the transmitter. The resistor R4 and capacitor C2 give us a represtation of this averaged over several cycles.

Similarly B2 provides a voltage representing the product of the current and the voltage in the load. In other words instantaneous output power. R5 and C3 give us a represenation of this averaged over a few cycles.

The third arbitrary behavioural voltage source, has an output voltage that is the ratio of output power over power supply power, or in other words, efficiency.
here is the result.
Class C Efficiency vs ontime diode and negative bias

We can see that the maximum efficiency (of about 47 percent in this case) occurs when the duty cycle is about that obtained 0.6 of the way through the run. That is 0.6 of 180 degrees or 108 degrees. There you have it: for maximum efficiency for a valve in Class C, we can turn it on for about 108 degrees of the carrier waveform cycle.

This is an outcome that agrees remarkably well with actual historic practice, given the crudeness of my model, but I do not regard it as definitive. I would define Class C this way:

A Class C amplifier is one suited to a narrow band fixed frequency signal. The valve is driven so as to provide a switching type of waveform without regard to distortion, and then the signal is recovered from the harmonics by a high Q tuned circuit called the Tank Circuit.

This is the 21st Century, and we are well into the solid state era. How does that affect this style of amplifier?

When I was a youngster, I spoke to a bloke who had built a low power AM Broadcast transmitter. It was for use on an island, and I believe the figure of 100 watts was mentioned. The Class C valve was an 807.

I asked him about the common practice (which he had followed) of placing the modulator on the very output of the transmitter. This is an expensive practice, as it requires two high powered amplifiers – a Class C RF amplifier and a (usually Class B push pull) audio amplifier.

“You have to place the modulator on the output because with Class C there is too much distortion” he said.

I contend that when simply put like this, this statement is nonsense. Can I justify that?

Answers to these two questions in the next post.

Footnote 1. F. Langford-Smith (ed) –  The Radiotron Designer’s Handbook Fourth Edition.
2. Douglas Self  – Audio Power Amplifier Design Handbook Chapter 6.

Postscript.
there has been a little delay in posting this, and that has given me the chance for a little more doodling. It has been interesting to check on the characteristic curves of a valve, the 6V6 beam power tetrode which I know was used as a Class C amplifier by amateurs in the old days. A 6V6 would give 4 watts in a Class A audio amplifier. I believe that they used to get 15 watts out of one in Class C. Here is a data sheet set of plate characteristic curves. I have added in red a line of best fit (good fit) to the part of the curve that represents the valve being “hard on”.
6V6 Hard On
It looks as if I was justified in choosing a switch with a resistor in series for my simple model above. I will return to this, and then I will try to stick to this century’s technology.

33 Negative Resistance Part 3

33 Negative Resistance Part 3 in which I realize that we need to distinguish between the negative resistance of a component and the resistance of a circuit. Maybe the solution to the tetrode oscillator problem was easier then it first looked. I also expose (but do not solve) a mistake I have made.

Last time I showed that the tetrode negative resistance oscillator, that would not work from a 90 volt supply with a dropping resistor, would work ok with a low impedance 45 volt supply. See earlier posts.

Later I realized that it had not been quite correct to say that the oscillator would not work with a 90 volt supply and a dropping resistor. In fact the originator of the circuit had been quite wrong when he complained that it would not work. It would work all right, it just would not start! This can be shown by starting it with a low impedance supply and letting it continue to run with the dropping resistor.

Cubic_osc_arse_kick_circuitThis is what I call my “Kick in the Arse” circuit. It starts off with the switch closed. This provides a low impedance 45 volt supply to establish 45 volts on the 2u cap C2. The oscillator starts. Then the switch opens, and the oscillator continues to operate perfectly well with what amounts to the original circuit!
Cubic_osc_arse_kick_plot

In fact it would have been much more easy than this to provide the required “starting kick”. Consider this circuit:
Cubic_osc_split_cap_circ
Of course, there would have had to be a power switch, or probably two power switches, as it would have been necessary to heat the cathode before applying the starting kick. Again, (in simulation) the oscillator starts and runs.

We might wonder if the simulation model is too “ideal”. A real 90 volt battery would have some series resistance. It might also have properties that dictate that it is not good practice to create large transient currents by placing a microfarad directly across it. I have tried placing a resistor in series with the supply. This resistance can be as high as 1k and the oscillator will still start. You can regard this 1k as modelling the battery intrinsic series resistance, or as an imposed surge current limiting resistor, or you can share the 1k amongst these concepts. It all depends on your line of thinking.

To further drive home the distinction between the negative resistance of a component and of the circuit as a whole, I set out to check the power supply input characteristics of this circuit. First, I tested my oscillator circuit model, and determined that it would start and run with a supply voltage range that exceeds 25 to 50 volts.

Then I set up a model to see how the supply current varied with supply voltage over this range.
Cubic_osc_circuit_current_circuit

The current source and the capacitor C2 provide a voltage ramp. The voltage controlled voltage source E1 follows that voltage and provides current that will not interfere with the current in C2. The resistor R1 has been included to allow C2 to present the lowest impedance shunt path for the oscillator signal. This enabled us to plot the output current of E1 with minimal high frequency ripple.

Let us limbo dance under the barrier to high frequencies presented by the capacitor.
Cubic_osc_circuit_current_plot2

I have relabelled the x axis to show the variable supply voltage, instead of the time, which was the true independent variable in the simulation. The red line is the curve generated by the simulation. The “spike” at the left side, is, I believe an artefact of my start-up transient. Indeed, although I cannot slow down the whole sweep very much, as the simulator is generating data for every cycle of the oscillator, and attempts to run the sweep very slowly lead to the generation of files that are too large for LTspice to handle, I can do a slowed down simulation of just the first couple of milliseconds of the sweep. If I reduce the sweep rate, the height of that initial current spike is also reduced.

The green line is a tangent that I have added by hand to determine the dynamic resistance of the oscillator as a load on the supply. The blue line is the load line for a 90 volt, 20k supply. It is evident that the operating point is completely stable. Note that the operating point is not at exactly 45 volts, but about 43 volts. That is not skin off anybody’s nose.

The ‘split capacitor circuit that I showed above, (repeated here to save you looking back)
Cubic_osc_split_cap_circ

exhibited a characteristic for the first 100 μs like this:
Cubic_osc_split_cap_plot1

The brown trace is the tetrode anode, and the blue trace is the junction of the two 2u capacitors. It occurred to me that if we run that blue plot for a longer time, we should see it sink to about 43 volts, the stable “operating point” that we determined with the load line above. I did the simulation, and this is what I got:
Split capacitor quiescent point

You can see that the quiescent point for the junction of the two 2u capacitors is about 45.5 volts. I cannot see how this can be different from the operating point we found with the load line (above). Can you?